1. Field of the Invention
This invention relates to the field of data processing systems. More particularly the invention relates to interconnect circuitry for data processing apparatus, the interconnect circuitry providing data routes via which one or more initiator devices such as a master may access one or more recipient devices such as a slave.
2. Background
Interconnects are used to provide connections between different components in data processing systems. They provide data routes via which one or more initiator devices may access one or more recipient device. An initiator device is simply a device that generates a transaction request, and therefore may be a master such as a processor or it may be another interconnect. A recipient device is simply a device that receives the transactions and it may be a slave such as a peripheral or it may also be another interconnect.
As systems become more complex with multiple processors communicating with each other and multiple devices, authors writing software for multiprocessor systems need detailed knowledge of the topology and latency of an architecture, in order to write software which ensures consistent behaviour of interacting processes across time. Even with this detailed knowledge this consistency is only achieved with some non-trivial effort and cost to performance.
It would be desirable to provide mechanisms that allowed a programmer to ensure consistent behaviour of interacting processes across time in a generic manner for an arbitrary architecture.
Barriers have been used for this purpose in co-pending US application for “Reduced Latency Barrier Transaction Requests in Interconnects” the entire contents of which is incorporated herein by reference. Barriers provide an effective way of maintaining an order between certain transaction requests within a transaction request stream. They do this by either not allowing the transaction requests that they control to overtake them or by blocking these transaction requests at an upstream point. Although this is an effective way of maintaining the order it does increase the latency of the system and requires control circuitry to control the barrier behaviour. It would be desirable to control the ordering of transactions without unduly increasing latency.